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Dynamic memory controller
188
NS9750 Hardware Reference
Table 120 shows the outputs from the memory controller and the corresponding
inputs to the 64M SDRAM (8Mx8, pins 13 and 14 used as bank selects).
Table 121 shows the outputs from the memory controller and the corresponding
inputs tot he 128M SDRAM (8Mx16, pins 13 and 14 used as bank selects).
Output address
(ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
14 BA1 11 11
13 BA0 10 10
12---
11 11 23 -
10 10/AP 22 AP
99 21 -
88 20 9
77 19 8
66 18 7
55 17 6
44 16 5
33 15 4
22 14 3
11 13 2
0 0 12 **
Table 120: Address mapping for 64M SDRAM (8Mx8, RBC)
Output address
(
ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
14 BA1 11 11
13 BA0 10 10
12---
Table 121: Address mapping for 128M SDRAM (8Mx16, RBC)