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Serial port control and status registers
660
NS9750 Hardware Reference
Serial Channel B/A/C/D Bit-rate register
Address: 9020 000C / 004C
9030 000C / 004C
The Serial Channel B/A/C/D Bit-rate register contains the serial channel timing
reference control bits and the data rate control bits.
D02 R THALF 0 Transmit FIFO half empty
Indicates that the transmit data FIFO contains room for at
least 16 bytes. THALF typically is used only in interrupt-
driven applications; this field is not used for DMA
operation.
The THALF status condition can be programmed to
generate an interrupt by setting the corresponding IE bit in
Serial Channel Control Register A.
D01 N/A Reserved N/A N/A
D00 R TEMPTY 0 Transmit FIFO empty
Indicates that the transmit data FIFO currently is empty.
TEMPTY simply reports the status of the FIFO; this bit
does not indicate that the character currently in the
Transmit Shift register has been transmitted.
Bits Access Mnemonic Reset Description
Table 386: Serial Channel B/A/C/D Status Register A
13121110987654321015 14
RICS N (divisor value)
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
RXSRC
TX
SRC
TX
EXT
RX
EXT
CLKMUX
TXC
INV
RXC
INV
SPC
POL
TDCR TICSEBIT
T
MODE
RDCR