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Ethernet Control and Status registers
362
NS9750 Hardware Reference
MII Management Write Data register
Address: A060 042C
Register bit assignment
D12:08 R/W DADR 0x00 MII PHY device address
Represents the 5-bit PHY device address field for
management cycles. Up to 32 different PHY devices
can be addressed.
D07:05 N/A Reserved N/A N/A
D04:00 R/W RADR 0x00 MII PHY register address
Represents the 5-bit PHY register address field for
management cycles. Up to 32 registers within a single
PHY device can be addressed.
Bits Access Mnemonic Reset Description
Table 220: MII Management Address register
Bits Access Mnemonic Reset Description
D31:16 N/A Reserved N/A N/A
D15:00 R/W MWTD 0x0000 MII write data
When this register is written, an MII Management
write cycle is performed using this 16-bit data along
with the preconfigured PHY device and PHY register
addresses defined in the MII Management Address
register (see page 361). The write operation completes
when the BUSY bit in the MII Management
Indicators register (see page 363) returns to 0.
Table 221: MII Management Write Data register
Reserved
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
MWTD