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97
Working with the CPU
Notes:
Alignment faults can write either 0b0001 or 0b0011 into Fault Status register
[3:0].
Invalid values can occur in the status bit encoding for domain faults. This
happens when the fault is raised before a valid domain field has been read
from a page table description.
Aborts masked by a higher priority abort can be regenerated by fixing the
cause of the higher priority abort, and repeating the access.
Alignment faults are not possible for instruction fetches.
The Instruction Fault Status register can be updated for instruction prefetch
operations
(MCR p15,0,Rd,c7,c13,1).
Fault Address register (FAR)
For load and store instructions that can involve the transfer of more than one word
(
LDM/STM, STRD, and STC/LDC), the value written into the Fault Address register
depends on the type of access and, for external aborts, on whether the access
crosses a 1 KB boundary. Table 40 shows the Fault Address register values for multi-
word transfers.
Domain Fault Address register
Alignment MVA of first aborted address in transfer
External abort on translation MVA of first aborted address in transfer
Translation MVA of first aborted address in transfer
Domain MVA of first aborted address in transfer
Permission MVA of first aborted address in transfer
External about for noncached reads, or
nonbuffered writes
MVA of last address before 1KB boundary, if any word of
the transfer before 1 KB boundary is externally aborted.
MVA of last address in transfer if the first externally
aborted word is after the 1 KB boundary.
Table 40: Fault Address register values for multi-word transfers