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687
IEEE 1284 Peripheral Controller
Forward Data FIFO Read register
Address: 9040 0010
Register bit assignment
Reverse FIFO Write register/Reverse FIFO Write Register — Last
Address: 9040 001C / 9040 0020
Both registers are 32 bits.
Bits Access Mnemonic Reset Description
D31:00 R FwDatFifoReadReg N/A Reads up to four bytes from the Forward Data
FIFO when in CPU mode. The CPU must read
the FIFO Status register (see page 684) to
determine how many bytes are remaining
before issuing the read.
Table 395: Forward Data FIFO Read register
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
FwDatFifoReadReg
FwDatFifoReadReg
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
RvFifoWriteReg
RvFifoWriteReg