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145
Memory Controller
Figure 54 shows a zero wait write followed by a zero wait read with default
turnaround between the transfers of one cycle. Three wait states are added to the
write transfer; five wait states are added to the read transfer. The five AHB
arbitration cycles for the read transfer include two wait states to allow the previous
write access to complete and the three standard wait states for the read transfer.
T5-T6 Memory controller processing.
T6-T7 Memory controller processing.
T7-T8 Static memory transfer address, chip select, and control signals
submitted to static memory.
Write data is read from AHB memory port.
Write enable inactive.
T8-T9 Write enable taken active.
Write data submitted to static memory.
T9-T10 Static memory control signals taken inactive.
T10-T11 Memory controller processing.
T11-T12 Static memory transfer 1, address, chip select, and control signals
submitted to static memory.
Write enable inactive.
Write data submitted to static memory.
T12-T13 Write enable taken active.
T13-T14 Static memory writes data 1.
Write enable taken inactive.
Cycle Description
Table 74: Read followed by write (both 0 wait) with no turnaround