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Timing
SDRAM burst read (16-bit), CAS latency = 3
Figure 105: SDRAM burst read (16-bit), CAS latency = 3 timing
Notes:
1 This is the bank and RAS address.
2 This is the CAS address.
pre act read lat lat d-A d-B d-C d-D d-E d-F d-G d-H
M9
M8
M7
M6
M5
M11
M4
M2
M1
Note-1 Note-2
clk_out<3:0>
data<31:16>
addr
data_mask<3:0>
dy_cs_n<3:0>*
ras_n
cas_n
we_n