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Serial port performance
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NS9750 Hardware Reference
Using the DMA controller
When using DMA, the processor need not interface with any of the serial port
registers for data flow; rather, the processor must interface with the DMA channel
registers and the DMA buffer descriptor block. To facilitate use of transmit DMA, the
ERXDMA field in Serial Channel B/A/C/D Control register A must be set active high.
When ERXDMA is set active high, disable the serial receiver interrupts.
Serial port performance
The serial ports have a finite performance limit on their ability to handle various
serial protocols. The performance is limited by the speed of the SYSCLK operating the
NS9750 ASIC. The configured speed for the internal PLL defines the BCLK rate; for
SPI, the serial port maximum rate is
BCLK/8.
Serial port control and status registers
The configuration registers for serial controller B are located at 0x9020_0000; the
configuration registers for serial controller A are located at
0x9020_0040. Table 382
shows a single, two-channel address map for serial controllers B and A.
All configuration registers must be accessed as 32-bit words and as single accesses
only. Bursting is not allowed.
Address Description
9020 0000 Channel B Control Register A
9020 0004 Channel B Control Register B
9020 0008 Channel B Status Register A
9020 000C Channel B Bit-Rate register
9020 0010 Channel B FIFO Data register
9020 0040 Channel A Control Register A
Table 382: Serial channel B & A configuration registers