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Ethernet Control and Status registers
390
NS9750 Hardware Reference
Register bit assignment
TX Error Buffer Descriptor Pointer register
Address: A060 0A20
Register bit assignment
Bits Access Mnemonic Reset Description
D31:08 N/A Reserved N/A N/A
D07:00 R/W TXRPTR 0x00 Contains a pointer to a buffer descriptor in the TX buffer
descriptor RAM.
Note: This pointer is the 8-bit physical address of the
TX buffer descriptor RAM, and points to the
first location of the four-location buffer
descriptor. The byte offset of this buffer
descriptor can be calculated by multiplying this
value by 4.
This is the buffer descriptor at which the
TX_WR logic
resumes processing when TCLER is toggled from low to
high in Ethernet General Control Register #2 (see
page 342).
Table 243: Transmit Recover Buffer Descriptor Pointer register
Bits Access Mnemonic Reset Description
D31:08 N/A Reserved N/A N/A
Table 244: TX Error Buffer Descriptor Pointer register
Reserved
TXERBD
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved