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619
Serial Control Module: UART
D26 R CGAP 0 Character GAP timer
Set when the enable receive character GAP timer is set in
Serial Channel Control Register B (see "RCGT" on page
616) and the timeout value defined in the Receive
Character GAP Timer register (see "Serial Channel B/A/
C/D Receive Character GAP Timer" on page 632) has
expired. This bit indicates that the maximum allowed time
has passed since the previous byte was placed into the
receive data buffer. The receive data buffer is closed under
this condition.
In DMA mode, this field is copied to bit [10] in the DMA
buffer descriptor.
25:22 R Not used 0x0 This field is always read as 0x0.
D21:20 R RXFDB 00 Receive FIFO data available
00 Full word
01 One byte
10 Half word
11 Three bytes
This field is valid only when RRDY = 1.
Identifies the number of valid bytes contained in the next
long word to be read from the Serial Channel FIFO Data
register. The next read of the FIFO can contain one, two,
three, or four valid bytes of data. This field must be read
before the FIFO is read to determine which bytes of the 4-
byte long word contain valid data.
Normal endian byte ordering rules apply to the Serial
Channel FIFO Data register.
D19 R DCD 0 Data carrier detect
0 Inactive
1 Active
Indicates the current state of the EIA data carrier detect
signal.
D18 R RI 0 Ring indicator
0 Inactive
1 Active
Indicates the current state of the EIA ring indicator signal.
Bits Access Mnemonic Reset Description
Table 369: Serial Channel B/A/C/D Status Register A