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Dynamic memory controller
194
NS9750 Hardware Reference
Table 128 shows the outputs from the memory controller and the corresponding
inputs to the 16M SDRAM (2Mx8, pin 14 used as a bank select).
Output address
(ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
14---
13 BA 20 20
12---
11---
10 10/AP 19 AP
99 18 -
88 17 -
77 16 8
66 15 7
55 14 6
44 13 5
33 12 4
22 11 3
11 10 2
009**
Table 127: Address mapping for 16M SDRAM (1Mx16, BRC)
Output address
(
ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
14 BA 21 21
13---
12---
11---
10 10/AP 20 AP
Table 128: Address mapping for 16M SDRAM (2Mx8, BRC)