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Noncachable instruction fetches
112
NS9750 Hardware Reference
Self-modifying code
A four-word buffer holds speculatively fetched instructions. Only sequential
instructions are fetched speculatively; if the ARM926EJ-S issues a nonsequential
instruction fetch, the contents of the buffer are discarded (flushed). In situations on
which the contents of the prefetch buffer might become invalid during a sequence of
sequential instruction fetches by the processor core (for example, turning the MMU
on or off, or turning on the ICache), the prefetch buffer also is flushed. This avoids
the necessity of performing an explicit Instruction Memory Barrier (IMB) operation,
except when self-modifying code is used. Because the prefetch buffer is flushed when
the ARM926EJ-S core issues a nonsequential instruction fetch, a branch instruction
(or equivalent) can be used to implement the required IMB behavior, as shown in this
code sequence:
LDMIA R0,{R1-R5} ; load code sequence into R1-R5
ADR R0,self_mod_code
STMIA R0,{R1-R5} ; store code sequence (nonbuffered region)
B self_mod_code ; branch to modified code
self_mod_code:
This IMB application applies only to the ARM926EJ-S processor running code from a
noncachable region of memory. If code is run from a cachable region of memory, or a
different device is used, a different IMB implementation is required. IMBs are
discussed in "Instruction Memory Barrier," beginning on page 113.
AHB behavior
If instruction prefetching is disabled, all instruction fetches appear on the AHB
interface as single, nonsequential fetches.
If prefetching is enabled, instruction fetches appear either as bursts of four
instructions or as single, nonsequential fetches. No speculative instruction fetching is
done across a 1 KB boundary.
All instruction fetches, including those made in Thumb state, are word transfers (32
bits). In Thumb state, a single-word instruction fetch reads two Thumb instructions
and a four-word burst reads eight instructions.