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Memory timing
808
NS9750 Hardware Reference
Static RAM sequential write cycles
Figure 116: Static RAM sequential write cycles
WTWR = 0
WWEN = 0
During a 32-bit transfer, all four byte_lane signals will go low.
During a 16-bit transfer, two byte_lane signals will go low.
During an 8-bit transfer, only one byte_lane signal will go low.
Note:
1 If the PB field is set to 0, the byte_lane signals will function as write enable signals and the we_n signal
will always be high.
M22M21
M24M23
M22M21
M20M19
M18M17
M16M15
Note1
CPU clock / 2
data<31:0>
addr<27:0>
st_cs_n<3:0>
we_n
byte_lane<3:0>
byte_lane[3:0] as WE*