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69
Working with the CPU
The invalidate TLB operations invalidate all the unpreserved entries in the
TLB.
The invalidate TLB single entry operations invalidate any TLB entry
corresponding to the modified virtual address given in
Rd, regardless of its
preserved state. See "R10: TLB Lockdown register," beginning on page 73,
for an explanation of how to preserve TLB entries.
Figure 19 shows the modified virtual address format used for invalid TLB single entry
operations.
Figure 19: R8: TLB Operations, MVA format
Note:
If either small or large pages are used, and these pages contain subpage
access permissions that are different, you must use four invalidate TLB
single entry operations, with the MVA set to each subpage, to invalidate
all information related to that page held in a TLB.
R9: Cache Lockdown register
Register R9 access the cache lockdown registers. Access this register using CRm = 0.
The Cache Lockdown register uses a cache-way-based locking scheme (format C) that
allows you to control each cache way independently.
Operation Data Instruction
Invalidate set-associative TLB SBZ
MCR p15, 0, Rd, c8, c7, 0
Invalidate single entry SBZ
MCR p15, 0, Rd, c8, c7. 1
Invalidate set-associative TLB SBZ
MCR p15, 0, Rd, c8, c5, 0
Invalidate single entry MVA
MCR p15, 0, Rd, c8, c5, 1
Invalidate set-associative TLB SBZ
MCR p15, 0, Rd, c8, c6, 0
Invalidate single entry MVA
MCR p15, 0, Rd, c8, c6, 1
Table 28: R8: Translation Lookaside Buffer operations
31 09
SBZ
Modified virtual address
10