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Working with the CPU
R0: ID code and cache type status registers
Register R0 access the ID register, and cache type register. Reading from R0 returns
the device ID, and the cache type, depending on the
opcode_2 value:
The
CRm field SHOULD BE ZERO when reading from these registers. Table 19 shows the
instructions you can use to read register R0.
Writing to register R0 is
UNPREDICTABLE.
R0: ID code
R0: ID code is a read-only register that returns the 32-bit device ID code. You can
access the ID code register by reading CP15 register R0 with the
opcode_2 field set to
any value other than 1 or 2. Note this example:
MRC p15, 0, Rd, c0, c0, {0, 3-7}; returns ID
Table 20 shows the contents of the ID code register.
opcode_2=0 ID value
opcode_2=1 instruction and data cache type
Function Instruction
Read ID code
MRC p15,0,Rd,c0,c0,{0, 3-7}
Read cache type
MRC p15,0,Rd,c0,c0,1
Table 19: Reading from register R0
Bits Function Value
[31:24] ASCII code of implementer trademark 0x41
[23:20] Specification revision 0x0
[19:16] Architecture (ARMv5TEJ) 0x6
[15:4] Part number 0x926
[3:0] Layout revision 0x0
Table 20: R0: ID code