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Static memory controller
122
NS9750 Hardware Reference
Write protection
Each static memory chip select can be configured for write-protection. SRAM usually
is unprotected and ROM devices must be write-protected (to avoid potential bus
conflict when performing a write access to ROM), but the P field in the Static Memory
Configuration register (see "Static Memory Configuration 0–3 registers" on page 230)
can be set to write-protect SRAM as well as ROM devices. If a write access is made to
a write-protected memory bank, an error is indicated by the
HRESP[1:0] signal. If a
write access is made to a memory bank containing ROM devices and the chip select is
not write-protected. An error is not returned and the write access proceeds as
normal. Note that this might lead to a bus conflict.
Extended wait transfers
The static memory controller supports extremely long transfer times. In normal use,
the memory transfers are timed using the Static Memory Read Delay register
(StaticWaitRd, see "Static Memory Read Delay 0–3 registers" on page 236) and Static
Memory Wait Delay register (StaticWaitWr, see "Static Memory Write Delay 0–3
registers" on page 238). These registers allow transfers with up to 32 wait states. If a
very slow static memory device has to be accessed, however, you can enable the
static configuration extended wait (EW) bit. When EW is enabled, the Static Extended
Wait register ("Static Memory Extended Wait register" on page 224) is used to time
both the read and write transfers. The Static Extended Wait register allows transfers
to have up to 16368 wait states.
Notes:
Using extremely long transfer times might mean that SDRAM devices are not
refreshed correctly.
Very slow transfers can degrade system performance, as the external
memory interface is tied up for long periods of time. This has detrimental
effects on time critical services, such as interrupt latency and low latency
devices; for example, video controllers.