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739
USB Controller Module
HcHCCA register
Address: 9010 1018
The HcHCCA register contains the physical address of the host controller
communication area (HCCA), which is a RAM area with a defined format. The host
controller driver determines the alignment restrictions by writing all 1s to HcHCCA
and reading the content of HcHCCA. The alignment is evaluated by examining the
number of zeros in the lower order bits. The minimum alignment is 256 bytes; bits 0
through 7, then, must always return 0 when read.
The host controller communication area holds the control structures and the
interrupt table that are accessed by both the host controller and the host controller
driver.
Register bit assignment
D00 R/W SO 0b Scheduling overrun
0 Ignore
1 Disable interrupt generation due to scheduling
overrun.
Bits Access Mnemonic Reset Description
Table 428: HcInterruptDisable register
Bits Access Mnemonic Reset Description
D31:08 R/W HCCA 0h Base address of the host controller communication area.
D07:00 R/W Not used 0 Must be written to 0.
Table 429: HcHCCA register
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
HCCA
Not used
HCCA