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Static memory controller
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NS9750 Hardware Reference
Figure 53: Read followed by write (both 0 wait) with no turnaround
Timing parameter Value
WAITRD 0
WAITOEN 0
WAITPAGE N/A
WAITWR 0
WAITWEN 0
WAITTURN 0
Table 73: Static memory timing parameters
Cycle Description
T0 AHB address provided to the memory controller.
T0-T1 AHB transaction processing.
T1-T4 Arbitration of AHB memory ports.
T4-T5 AHB write address provided to memory controller.
Table 74: Read followed by write (both 0 wait) with no turnaround
ADDR
DATAIN
B
OEOUT
A 0
D(A)
STCSOUT_n
DATAOUT
D(B)
WEOUT_n
DATAEN_n
clk_out
T0 T1 T2 T3 T4 T5 T6 T7 T10 T11T8 T9 T12 T13 T14