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155
Memory Controller
Access: Read, little endian, 16-bit
external bus
External data mapping on to system
databus
Internal
transfer
width
HRDATA to DATA
HSIZE
[2:0]
HADDR
[1:0]
ADDROUT
[0]
BLSOU
T [1:0]
[31:24] 23:16] [15:8] [7:0]
Word (2
transfers
010 -- 1
0
00
00
[15:8]
-
[7:0]
-
-
[15:8]
-
[7:0]
Halfword 001 1- 1 00 [15:8] [7:0] - -
Halfword 001 0- 0 00 - - [15:8] [7:0]
Byte 000 11 1 01 [15:8] - - -
Byte 000 10 1 10 - [7:0] - -
Byte 000 01 0 01 - - [15:8] -
Byte000000 10---[7:0]
Table 80: Little endian read, 16-bit external bus
Access: Read, little endian, 32-bit
external bus
External data mapping on to system
databus
Internal
transfer
width
HRDATA to DATA
HSIZE
[2:0]
HADDR
[1:0]
BLSOUT
[3:0]
[31:24] [23:16] [15:8] [7:0]
Word 010 -- 0000 [31:24] [23:16] [15:8] [7:0]
Halfword 001 1- 0011 [31:24] [23:16] - -
Halfword (2
transfers)
001 0- 1100 - - [15:8] [7:0]
Byte 000 11 0111 [31:24] - - -
Table 81: Little endian read, 32-bit external bus