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BBus DMA Controller
D27:26 R/W MODE 0 Fly-by mode
00 Fly-by write (peripheral-to-memory)
01 Fly-by read (memory-to-peripheral)
10 Undefined
11 Undefined
Defines the fly-by transfer mode.
D25:24 R/W BTE 0 Burst transfer enable
00 1 operand
01 2 operands
10 4 operands (Recommended)
11 Reserved
Determines whether the DMA channel can use burst
transfers through the bus. This configuration applies to
both buffer descriptor and peripheral data access.
D23 R/W REQ 0 Always set to 0.
D22 R/W BDR 0 Buffer descriptor refetch
Causes the DMA controller to refetch the current buffer
descriptor before proceeding. This is necessary to
retransmit erroneous packets sent from the USB device to
the USB host.
Hardware automatically clears this field after refetching
the buffer descriptor.
D21 R/W SINC_N 0 Source address increment field
0 Increment source address pointer
1 Do not increment source address pointer
Controls whether the source address pointers are
incremented after each DMA transfer. The DMA
controller uses this field in all modes whenever referring
to a memory address.
D20:18 R/W Not used 0 N/A
D17:16 R/W SIZE 0 Size field
Must always be set to 0.
The datapath between the BBus and AHB bus is 32 bits. If
the system memory bus is less than 32 bits, the translation
is handled in the memory controller.
Bits Access Mnemonic Reset Description
Table 313: BBus DMA Control register bit definition