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USB Controller Module
USB Device Endpoint FIFO Control and Data registers
Table 447 provides the addresses for the endpoint registers found in the application
logic that interfaces to the USB device block.
D03:00 R/W EDNBR 4’h0 Endpoint number
Bits Access Mnemonic Reset Description
Table 446: Endpoint Descriptor register (for endpoint descriptors 0–11)
Address Register
9010 3000 FIFO Interrupt Status 0
9010 3004 FIFO Interrupt Enable 0
9010 3010 FIFO Interrupt Status 1
9010 3014 FIFO Interrupt Enable 1
9010 3020 FIFO Interrupt Status 2
9010 3024 FIFO Interrupt Enable 2
9010 3030 FIFO Interrupt Status 3
9010 3034 FIFO Interrupt Enable 3
9010 3080 FIFO Packet Control #1
9010 3084 FIFO Packet Control #2
9010 3088 FIFO Packet Control #3
9010 308C FIFO Packet Control #4
9010 3090 FIFO Packet Control #5
9010 3094 FIFO Packet Control #6
9010 3098 FIFO Packet Control #7
9010 309C FIFO Packet Control #8
9010 30A0 FIFO Packet Control #9
Table 447: USB Device Endpoint FIFO Control registers address map