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549
I2C Master/Slave Interface
Status Receive Data register
Address: 9050 0000
The Status Receive Data register (STATUS_RX_DATA_REG) is the primary interface
register for receipt of data between the NS9750 BBus and I
2
C bus. This register is
read only.
Register bit assignment
Bits Access Mnemonic Reset Description
D31:16 N/A Reserved N/A N/A
D15 R BSTS N/A Bus status (master only)
0Bus is free
1 Bus is occupied
D14 R RDE N/A Receive data enable (rx_data_en)
Received data is available.
D13 R SCMDL N/A Slave command lock
The Slave Command register is locked.
D12 R MCMDL N/A Master command lock
The Master Command register is locked.
D11:08 R IRQCD N/A Interrupt codes
(irq_code)
The interrupt is cleared if this register is read. See
"Interrupt Codes" on page 553 for more information.
D07:00 R RXDATA N/A Received data from I
2
C bus
Together with a
RX_DATA interrupt, this register provides
a received byte (see Table 342: "Master/slave interrupt
codes" on page 553).
Table 338: STATUS_REG and RX_DATA_REG
SCMDL
MCMDL
IRQCD RXDATA
13121110987654321015
14
BSTS RDE
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved