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431
PCI-to-AHB Bridge
Register bit assignment
PCI Configuration 3 register
Address: A030 001C
The PCI Configuration 3 register contains the values that will be read from the PCI
Max_Lat, PCI Min_Gnt, and PCI Interrupt Pin registers.
Change these fields only during system initialization, when there is no PCI activity. In
a system where NS9750 is not the host, these fields must be programmed within 2
25
PCI clocks of
RST# being negated. This is the time allowed from RST# negated to the
first configuration cycle on the PCI bus.
Register bit assignment
Bits Access Mnemonic Reset Description
D31:16 R/W SUBSYSTEM_ID 0x0000 Subsystem ID value
Value to be inserted into the PCI Subsystem ID
register. Defaults to
0x0000.
D15:00 R/W SUBVENDOR_ID 0x0000 Subvendor ID value
Value to be inserted into the PCI Subvendor ID
register. Defaults to
0x0000.
Table 266: PCI Configuration 2 register
Bits Access Mnemonic Reset Description
D31:24
Read only;
hard-wired to
0
Reserved N/A N/A
Table 267: PCI Configuration 3 register
Reserved
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
MIN_GRANT
MAX_LATENCY
INTERRUPT_PIN