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777
USB Controller Module
FIFO Interrupt Enable 1 register
Address: 9010 3014
Register bit assignment
Bits Access Mnemonic Reset Description
D31 R/W ACK6 0 Generate an interrupt when ACK6 in FIFO Interrupt
Status 1 register is asserted.
D30 R/W NACK6 0 Generate an interrupt when NACK6 in FIFO Interrupt
Status 1 register is asserted.
D29 R/W ERROR6 0 Generate an interrupt when ERROR6 in FIFO Interrupt
Status 1 register is asserted.
D28:24 N/A Reserved N/A Not valid in DMA mode.
D23 R/W ACK5 0 Generate an interrupt when ACK5 in FIFO Interrupt
Status 1 register is asserted.
D22 R/W NACK5 0 Generate an interrupt when NACK5 in FIFO Interrupt
Status 1 register is asserted.
D21 R/W ERROR5 0 Generate an interrupt when ERROR5 in FIFO Interrupt
Status 1 register is asserted.
D20:16 N/A Reserved N/A Not valid in DMA mode.
D15 R/W ACK4 0 Generate an interrupt when ACK4 in FIFO Interrupt
Status 1 register is asserted.
D14 R/W NACK4 0 Generate an interrupt when NACK4 in FIFO Interrupt
Status 1 register is asserted.
D13 R/W ERROR4 0 Generate an interrupt when ERROR4 in FIFO Interrupt
Status 1 register is asserted.
D12:08 N/A Reserved N/A Not valid in DMA mode.
Table 455: FIFO Interrupt Enable 1 register
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
ERROR
4
Reserved
ACK4
NACK
4
Reserved
ACK3
NACK
3
ERROR
3
ACK6
NACK
6
ERROR
6
ERROR
5
NACK
5
ACK5
Reserved