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AHB interface
568
NS9750 Hardware Reference
AHB interface
The AHB interface includes the AHB slave interface and the AHB master interface.
AHB master and slave interfaces
The AHB master interface transfers display data from memory to the LCD controller
DMA FIFOs.
The AHB slave interface connects the LCD to the AHB bus and provides CPU accesses
to the registers and palette RAM. The LCD controller AHB slave interface supports
these features:
Dual DMA FIFOs and associated control logic
The pixel data accessed from memory is buffered by two DMA FIFOs, which can be
controlled independently to cover single and dual panel LCD types. Each FIFO is 64
words deep by 32 bits wide, and can be cascaded to form a 128-word deep FIFO in
single panel mode. The FIFO input ports are connected to the AHB interface and the
output port feeds the pixel serializer.
Synchronization logic is used to transfer the pixel data from the AHB
HCLK domain to
the
CLCDCLK clock domain. The DMA FIFOs are clocked by HCLK.
The water level marks within each FIFO are set such that each FIFO requests data
when at least four locations become available.