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PCI-to-AHB Bridge
PCI Arbiter Configuration register
Address: A030 0000
The PCI Arbiter Configuration register enables and disables each of the three external
PCI bus masters. The internal PCI-to-AHB bridge is always enabled.
Register bit assignment
Bits Access Mnemonic Reset Description
D31:04
Read only;
hard-wired
to 0
Reserved N/A N/A
D03 R/W PCIEN_M3 0 External master 3 enable
0 Disable (default)
1 Enable
If the master becomes broken, toggle low -> high to
re-enable.
D02 R/W PCIEN_M2 0 External master 2 enable
0 Disable (default)
1 Enable
If the master becomes broken, toggle low -> high to
re-enable.
D01 R/W PCIEN_M1 0 External Master 1 Enable
0 Disable (default)
1 Enable
If the master becomes broken, toggle low-> high to re-
enable.
Table 260: PCI Arbiter Configuration register
Reserved
PCI
EN_
M3
PCI_
CTL_
RSC_n
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
PCI
EN_
M2
PCI
EN_
M1