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Dynamic memory controller
166
NS9750 Hardware Reference
Table 93 shows the outputs from the memory controller and the corresponding inputs
to the 64M SDRAM (2Mx32, pins 13 and 14 used as bank selects).
33 15 5
22 14 4
11 13 3
00 12 2
Output address
(
ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
14 BA1 11 11
13 BA0 10 10
12---
11---
10 10/AP 22 AP
99 21 -
88 20 -
77 19 9
66 18 8
55 17 7
44 16 6
33 15 5
22 14 4
11 13 3
00 12 2
Table 93: Address mapping for 64M SDRAM (2Mx32, RBC)
Output address
(
ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
Table 92: Address mapping for 16M SDRAM (2Mx8, RBC)