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581
LCD Controller
Horizontal timing restrictions
DMA requests new data at the beginning of a horizontal display line. Some time must
be allowed for the DMA transfer and for the data to propagate down the FIFO path in
the LCD interface. The data path latency forces some restrictions on the usable
minimum values for horizontal porch width in STN mode. The minimum values are
HSW = 2 and HBP = 2. Table 351 shows the recommended minimum values for STN
displays:
If sufficient time is given at the beginning of the line (for example, HSW is set to 6
and HBP is set to 10), data will not become corrupted for PCD = 4 (minimum value for
dual panel mode).
D15:08 R/W HSW 0x00 Horizontal synchronization pulse width
Width of the
CLLP signal in CLCP periods. Program
this field with value minus 1.
HSW specifies the pulse width of the line clock in
passive mode, or the horizontal synchronization pulse
in active mode.
D07:02 R/W PPL 0x00 Pixels-per-line
Actual pixels-per-line = 16 * (PPL+1)
The PPL field specifies the number of pixels in each
line or row of the screen. PPL is a 6-bit value that
represents between 16 and 1024 PPL. PPL counts the
number of pixel clocks that occur before HFP is
applied (program the value required divided by 16,
minus 1).
D01:00 N/A Reserved N/A N/A
Mode HSW HBP HFP Panel clock divisor (PCD)
Single panel STN mode3551 (
CLCDCLK/3)
Dual panel STN mode3555 (CLCDCLK/7)
Table 351: Minimum recommended values for STN displays
Bits Access Mnemonic Reset Description
Table 350: LCDTiming0 register