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Dynamic memory controller
180
NS9750 Hardware Reference
Table 110 shows the outputs from the memory controller and the corresponding
inputs to the 128M SDRAM (8Mx16, pins 13 and 14 used as bank selects).
Table 111 shows the outputs from the memory controller and the corresponding
inputs to the 128M SDRAM (16Mx8, pins 13 and 14 used as bank selects).
Output address
(ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
14 BA1 23 23
13 BA0 24 24
12---
11 11 22 -
10 10/AP 21 AP
99 20 -
8 8 19 10
77 18 9
66 17 8
55 16 7
44 15 6
33 14 5
22 13 4
11 12 3
00 11 2
Table 110: Address mapping for 128M SDRAM (8Mx16, BRC)
Output address
(
ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
14 BA1 25 25
13 BA0 24 24
12 12 - -
Table 111: Address mapping for 128M SDRAM (16Mx8, BRC)