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Ethernet Control and Status registers
386
NS9750 Hardware Reference
D24 R/C RXOVFL_STAT 0 Assigned to RX interrupt.
RX status FIFO overflowed.
D23 R/C RXBUFC 0 Assigned to RX interrupt.
I bit set in receive Buffer Descriptor and buffer closed.
D22 R/C RXDONEA 0 Assigned to RX interrupt.
Complete receive frame stored in pool A of system
memory.
D21 R/C RXDONEB 0 Assigned to RX interrupt.
Complete receive frame stored in pool B of system
memory.
D20 R/C RXDONEC 0 Assigned to RX interrupt.
Complete receive frame stored in pool C of system
memory.
D19 R/C RXDONED 0 Assigned to RX interrupt.
Complete receive frame stored in pool D of system
memory.
D18 R/C RXNOBUF 0 Assigned to RX interrupt.
No buffer is available for this frame due to one of
these conditions:
All four buffer rings being disabled
All four buffer rings being full
No available buffer big enough for the frame
D17 R/C RXBUFFUL 0 Assigned to RX interrupt.
No buffer is available for this frame because all four
buffer rings are disabled or full.
D16 R/C RXBR 0 Assigned to RX interrupt.
New frame available in the RX_FIFO. This bit is used
for diagnostics.
D15:07 N/A Reserved N/A N/A
Bits Access Mnemonic Reset Description
Table 240: Ethernet Interrupt Status register