Filter
Top Products
PCI system configurations
458
NS9750 Hardware Reference
Device selection for configuration
The NS9750 IDSEL pin is used as a chip select during PCI configuration transactions. If
the bridge’s configuration registers are being programmed using the AHB bus, NS9750
must be set as Device 0 (see Figure 72, "System connections to NS9750 — Internal
arbiter and central resources," on page 456, which shows
IDSEL connected to AD[11]
and which configures NS9750 as PCI Device 0).
If the bridge’s configuration registers are programmed using an external PCI device,
NS9750 can be configured as any PCI device number (see Figure 73, "System
connections to NS9750 — External arbiter and central resources," on page 457, which
shows
IDSEL connected to AD[12] and which configured NS9750 as Device 1). Any
accesses from the AHB bus to the bridge’s configuration registers, however, must be
done as Device 0.
PCI interrupts
NS9750 can serve as the interrupt controller for all four PCI interrupts. These
interrupts go directly to the interrupt controller in the System Control module.
Because these interrupts are open-drain type signals, the transition from low to high
is relatively slow once the source of the interrupt is cleared.
SERR# input can also
cause an interrupt through
PCISERR (in the PCI Arbiter Interrupt Status register).
Important:
The system software must provide adequate time for the interrupt signals
and
SERR# to rise before re-enabling them.
If an external interrupt controller is used, NS9750 can drive INTA# using INTA2PCI (in
the PCI Miscellaneous Support register).
PCI central resource functions
NS9750 provides several PCI central resource functions when NS9750’s
PCI_CENTRAL_RSC_n pin is pulled low (see Figure 72):
RST# to the PCI system is driven through NS9750. RST# is asserted
asynchronously and negated synchronously to the PCI clock.
RST# is driven
from the system reset to NS9750 and the
PCI bit in the Reset and Sleep
Control register in the System Control Module.
SERR# is configured as an input.