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Ethernet MAC
322
NS9750 Hardware Reference
If any of the counters roll over, an associated carry bit is set in the Carry 1 (CAR1) or
Carry 2 (CAR2) registers (see "General Statistics registers," beginning on page 377).
Any statistics counter overflow can cause the
STOVFL bit in the Ethernet Interrupt
Status register (see page 385) to be set if its associated mask bit is not set in Carry
Mask Register 1 or Carry Mask Register 2 (see "General Statistics registers," beginning
on page 377).
The counters support a clear on read capability that is enabled when
AUTOZ is set to 1
in the Ethernet General Control Register #2.