Filter
Top Products
www.digiembedded.com
163
Memory Controller
Word transfers are the widest transfers supported by the memory controller. Any
access tried with a size larger than a word generates an error response.
Address mapping
This section provides tables that show how AHB address bus addresses map to the
external dynamic memory address
ADDROUT[14:0] for different memory configurations
and bus widths. The address mapping is selected by programming the address
mapping bits in the Dynamic Memory Configuration registers (see "Dynamic Memory
Configuration 0–3 registers" on page 225).
The information provided includes:
Memory controller output address (ADDROUT). Indicates the address lines
output from the memory controller.
Memory device connections. Indicate the device signals that must be
connected to the memory controller
AddrOut lines.
AHB addresses to row address. Indicates the input HADDR address bits used
from the AHB transfer for the row access.
AHB address to column address. Indicates the input HADDR address bits
used from the AHB transfer for the column access.
Notes:
For all tables in this section:
– ** indicates that the bit is controlled by the SDRAM controller. The SDRAM
controller always transfers 32-bits of data at a time. For chip selects with a
16-bit wide databus, the SDRAM controller performs two transfers: a column
transfer with the lowest bit set to 0 and a column transfer with the lowest
bit set to 1.
– BA, BA0, and BA1 indicate the bank address signals. AP indicates the auto
precharge signal (usually, address bit 10).
Separate tables are provided for two different address mapping schemes:
row, bank, column (RBC) or bank, row, column (BRC), and for 32-bit and 16-
bit wide buses:
– 32-bit wide databus address mappings, SDRAM (RBC) (see "32-bit wide
databus address mappings, SDRAM (RBC)" on page 164). These address
mappings are used for 32-bit data bus chip select with SDR-SDRAM memory