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BBus Bridge
Interrupt aggregation
All the peripherals on the BBus, as well as AHB DMA channels 1 and 2 in the BBus
bridge, can interrupt the CPU when attention is required. These interrupts are
aggregated in the BBus bridge, and a single interrupt is presented to the System
Control Module on the
bbus_int signal.
This function is performed in the BBus bridge because it allows the processor to
quickly identify which BBus peripheral(s) is requesting attention. (See "BBus Bridge
Interrupt Status register" on page 498 for more information.)
Note:
The interrupt(s) must be serviced in the peripheral in which the
interrupt(s) originated.
Bandwidth requirements
A single AHB timeslot is sufficient to support the ideal maximum bandwidth of the
BBus peripherals plus overhead for DMA buffer descriptors. The maximum case occurs
with four SPI masters, IEEE 1284, and either USB device or USB host.
The SPI master interfaces support a maximum of 6.25 Mbps of full duplex
traffic.
The IEEE-1284 interface supports a maximum of 2 Mbps of full duplex
traffic.
The USB supports a maximum of 12 Mbps of full duplex traffic.
The total peripheral bandwidth is 64Mbps. Adding 8 Mbps for DMA buffer descriptors
brings the total requirement to 9 MBps, less than one AHB timeslot with a full 16-slot
rotation.
Important:
Be aware that the AHB DMA channels and the BBus peripherals share an
AHB timeslot. The BBus peripherals are always given a higher priority than
the AHB DMA channels. The busier the BBus peripherals, then, the less
available bandwidth for the AHB DMA channels.