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447
PCI-to-AHB Bridge
CardBus Socket Mask register
Address: A030 1004
The CardBus Socket Mask register is used for CardBus applications only, and contains
the interrupt enable bits for each of the bits in the CardBus Socket Event register.
Bits Access Mnemonic Reset Description
D31:04 Hardwired to
0
Reserved N/A N/A
D03 R/C PWR_CHG 0 Set when the PWR_CYC bit in the CardBus
Socket Present State register changes.
This bit can also be set by writing a 1 to the
FPWR_CHG bit in the CardBus Socket Force
Event register.
D02 R/C CCD2_CHG 0 Set when the
CCD#2 signal changes. Changes
during card interrogation (when the
INTERROGATE bit is set to 1 in the CardBus
Miscellaneous Support register) are ignored.
This bit can also be set by writing a 1 to the
FCCD2_CHG bit in the CardBus Socket Force
Event register.
D01 R/C CCD1_CHG 0 Set when the
CCD#1 signal changes. Changes
during card interrogation (when the
INTERROGATE bit is set to 1 in the CardBus
Miscellaneous Support register) are ignored.
This bit can also be set by writing a 1 to the
FCCD1_CHG bit in the CardBus Socket Force
Event register.
D00 R/C
CSTSCHG_CHG
0 Set when the CSTSCHG signal changes from low
to high. Changes during card interrogation (when
the INTERROGATE bit is set to 1 in the CardBus
Miscellaneous Support register) are ignored.
This bit can also be set by writing a 1 to the
FCSTSCHG_CHG bit in the CardBus Socket
Force Event register.
Table 280: CardBus Socket Event register