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BBus slave and DMA interface
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NS9750 Hardware Reference
D23 R/W FDBGM 0x0 Forward data FIFO byte gap mask
(FwDatFifoByteGapMask)
0 Mask the interrupt
1 Enable the interrupt
D22 R/W FCBGM 0x0 Forward command FIFO byte gap mask
(FwCmdFifoByteGapMask)
0 Mask the interrupt
1 Enable the interrupt
D21 R/W FDMBM 0x0 Forward data FIFO max buffer mask
(FwDatFifoMaxBufMask)
0 Mask the interrupt
1 Enable the interrupt
D20 R/W FCMBM 0x0 Forward command FIFO max buffer mask
(FwCmdFifoMaxBufMask)
0 Mask the interrupt
1 Enable the interrupt
D19 R/W FDRIM 0x0 Forward data FIFO ready interrupt mask
(FwDatFifoRdyInterruptMask)
0 Mask the interrupt
1 Enable the interrupt
D18 R/W FCRIM 0x0 Forward command FIFO ready interrupt mask
(FwCmdFifoRdyInterruptMask)
0 Mask the interrupt
1 Enable the interrupt
D17 R/W I1M 0x0 Peripheral controller interrupt 1 mask
0 Mask the interrupt
1 Enable the interrupt
D16:11 N/A Reserved N/A N/A
D10 R/C RFRI 0x1 Reverse FIFO ready interrupt (RvFifoRdyInterrupt)
Asserted when the reverse FIFO can accept the number of
bytes specified in the reverse ready threshold bit in the
IEEE 1284 General Configuration register.
D09 N/A Reserved 0x1 N/A
D08 N/A Reserved 0x0 N/A
Bits Access Mnemonic Reset Description
Table 392: Interrupt Status and Control register