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PCI timing
818
NS9750 Hardware Reference
Internal PCI arbiter timing
Figure 121: Internal PCI arbiter timing
PCI burst write from NS9750 timing
Figure 122: PCI burst write from NS9750 timing
Note:
The functional timing for trdy_n and devsel_n shows the fastest possible
response from the target.
data0 addr
P1
P2
P3
Master 1 CycleMaster 1 CycleMaster 2 CycleMaster 2 CycleMaster 1 CycleMaster 1 Cycle
Switch MasterSwitch Master
addr data1 data2 data0 addr data0
pci_clk_in
frame_n
irdy_n
ad[31:0]
pci_arb_req_1_n
pci_arb_req_2_n
pci_arb_gnt_1_n
pci_arb_gnt_2_n
P3P2
P3P2
P1
P1
P5P1P4
P1
byte enablescmd
addr data0 data1 data2 data3 data4 data5 data6 data7
pci_clk_in
frame_n
ad[31:0]
cbe_n[3:0]
irdy_n
trdy_n
devsel_n