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239
Memory Controller
Static Memory Turn Round Delay 0–3 registers
Address: A070 0218 / 0238 / 0258 / 0278
The Static Memory Turn Round Delay 0–3 registers allow you to program the number
of bus turnaround cycles. It is recommended that these registers be modified during
system initialization, or when there are no current or outstanding transactions. Wait
until the memory controller is idle, then enter low-power or disabled mode.
Register bit assignment
To prevent bus contention on the external memory databus, the WAITTURN field
controls the number of bus turnaround cycles added between static memory read and
write accesses.
The WAITTURN field also controls the number of turnaround cycles between static
memory and dynamic memory accesses.
Bits Access Mnemonic Description
D31:04 N/A Reserved N/A (do not modify)
D03:00 R/W WTTN Bus turnaround cycles (WAITTURN)
0000–1110 (n+1) HCLK turnaround cycles, where bus
turnaround time is (WAITTURN+1) x t
HCLK
1111 16 HCLK turnaround cycles (reset value on reset_n).
Table 165: Static Memory Turn Round Delay 0–3 registers
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
Reserved WTTN