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207
Memory Controller
Status register
Address: A070 0004
The Status register provides memory controller status information.
Register bit assignment
Configuration register
Address: A070 0008
Bits Access Mnemonic Description
D31:03 N/A Reserved N/A (do not modify)
D02 R SA Self-refresh acknowledge (SREFACK)
0 Normal mode
1 Self refresh mode (reset value on
reset_n)
Indicates the memory controller operating mode.
D01 R WBS Write buffer status
0 Write buffers empty (reset value on
reset_n)
1 Write buffers contain data
Enables the memory controller to enter low-power mode or disabled
mode clearly.
D00 R BUSY Busy
0 Memory controller is idle (reset value on
HRESETn)
1 Memory controller is busy performing memory transactions,
commands, or auto-refresh cycles, or is in self-refresh mode
(reset value on
reset_n and HRESETn)
Ensures that the memory controller enters the low-power or disabled
state cleanly by determining whether the memory controller is busy.
Table 139: Status register
BUSY
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
Reserved
SA WBS