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583
LCD Controller
LCDTiming2 register
Address: A080 0008
The LCDTiming2 register provides controls for the timing signals.
D23:16 R/W VFP 0x00 Vertical front porch
Number of inactive lines at the end of the frame,
before vertical synchronization period. Program this
field to zero on passive displays, to avoid reduced
contrast.
VFP specifies the number of blank lines to insert at the
end of each frame. Once a complete frame of pixels is
transmitted to the LCD display, the value in VFP
counts the number of horizontal synchronization lines
to wait. After the count has elapsed, the vertical
synchronization (
CLFP) signal is asserted in active
mode, or extra line clocks are inserted as specified by
the VSW field in passive mode. VFP generates from
0 – 255
CLLP cycles.
D15:10 R/W VSW 0x00 Vertical synchronization pulse width
Number of horizontal synchronization lines. This
value must be small (for example, program to 0) for
passive STN LCDs. Program this field to the number
of lines required minus one. The higher the value, the
worse the contrast on STN LCDs.
VSW specifies the pulse width of the vertical
synchronization pulse. This field is programmed to
the number of horizontal synchronization lines minus
one.
D09:00 R/W LPP 0x000 Lines per panel
Number of active lines per screen. Program this field
to number of lines required minus 1.
LPP specifies the total number of lines or rows on the
LCD panel being controlled; between 1 and 1024 lines
are allowed. This field is programmed with the
number of lines per LCD panel minus 1.
For dual panel displays, this field is programmed with
the number of lines on each of the upper and lower
panels.
Bits Access Mnemonic Reset Description
Table 352: LCDTiming1 register