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Serial port control and status registers
630
NS9750 Hardware Reference
Reading from the receive register empties the receive FIFO. Data is available when
the RRDY bit is set in Serial Channel Status Register A. The RXFDB field in Serial
Channel Status Register A identifies how many bytes are available to be read. Reading
the Serial Channel FIFO Data register automatically clears the RRDY bit in Serial
Channel Status Register A.
Register bit assignment
Serial Channel B/A/C/D Receive Buffer GAP Timer
Address: 9020 0014 / 0054
9030 0014 / 0054
The Receive Buffer GAP Timer closes out a receive serial data buffer. This timer can
be configured to provide an interval in the range of 34.7uS to 2.27 S. The timer is
reset when the first character is received in a new buffer. New characters are
received while the timer operates; when the timer reaches its programmed
threshold, the receive buffer is closed.
Bits Access Mnemonic Reset Description
D31:00 R/W DATA 0x00000000 Serial channel FIFO data field.
Table 373: Serial Channel B/A/C/D FIFO Data register
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
DATA
DATA
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Not used
Buffer GAP timer (BT)
TRUN