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About the PCI-to-AHB Bridge
408
NS9750 Hardware Reference
DETECTED PARITY ERROR bit in the PCI Status register is set. For address parity errors,
the
SIGNALED TARGET ABORT bit in the PCI Status register is set.
For data parity checking on writes, the entire burst is discarded if any word in the
burst has a parity error.
AHB address decoding and translation
The PCI-to-AHB bridge supports these four AHB address spaces:
PCI memory (0x8000_0000->0x8FFF_FFFF; 256 MB)
PCI IO (0xA000_0000->0xA00F_FFFF; 1 MB)
PCI CONFIG_ADDR register (0xA010_0000)
PCI CONFIG_DATA register (0xA020_0000)
The bridge supports AHB to PCI memory address translation using the PCI Bridge AHB
to PCI Memory Address Translate 0/1 (see page 437 and page 438) and PCI Bridge
Address Translation Control (see page 441) registers. The address translation scheme
breaks the 256 MB memory window from AHB to PCI into eight 32 MB subwindows that
can be translated individually.
The
PALTxVAL fields in the PCI Bridge AHB to PCI Memory Address Translate 0/1
registers control the translation for each of the eight subwindows. For example, if
PALT0VAL is set to 0x75, an access to 0x8000_0000 on the AHB bus is mapped to 0xEA00_0000
in the PCI bus. The
PALT_EN bit in the PCI Bridge Address Translation Control register
determines whether AHB to PCI address translation is enabled:
When set to 1, PALT_EN enables address translation.
When set to 0, no address translation takes place, and the AHB and PCI
addresses are identical.
Address translation also is provided for accesses to PCI IO space from the AHB bus.
The translation process is similar to memory address translation, with this exception:
the
PALT8VAL field translates the 1 MB window dedicated to PCI IO space to another 1
MB IO window on the PCI bus. When
PALT_EN is set to 1, IO translation is enabled.
PCI address decoding and mapping
The PCI-to-AHB bridge uses six Base Address registers (BAR), defined in the PCI
Configuration register (see Table 254, “PCI/bridge configuration registers,” on
page 413), to determine the range of PCI addresses to which the bridge responds. The