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Ethernet Control and Status registers
360
NS9750 Hardware Reference
Clocks field settings
MII Management Command register
Address: A060 0424
Register bit assignment
Note:
If both SCAN and READ are set, SCAN takes precedence.
CLKS field Divisor
AHB bus clock for 2.5 MHz AHB bus clock for 12.5 MHz
000 4 50 MHz
001 4 50 MHz
010 6 75 MHz
011 8 100 MHz
100 10
101 20 50 MHz
110 30 75 MHz
111 40 100 MHz
Bits Access Mnemonic Reset Description
D31:02 N/A Reserved N/A N/A
Table 219: MII Management Command register
Reserved
READ
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
SCAN