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Memory Management Unit (MMU)
98
NS9750 Hardware Reference
Compatibility issues
To enable code to be ported easily to future architectures, it is
recommended that no reliance is made on external abort behavior.
The Instruction Fault Status register is intended for debugging purposes
only.
Domain access control
MMU accesses are controlled primarily through the use of domains. There are 16
domains, and each has a two-bit field to define access to it. Client users and Manager
users are supported.
The domains are defined in the R3: Domain Access Control register. Figure 15, "R3:
Domain Access Control register," on page 61 shows how the 32 bits of the register are
allocated to define the 16 two-bit domains.
Table 41 shows how the bits within each domain are defined to specify access
permissions.
Table 42 shows how to interpret the access permission (AP) bits, and how the
interpretation depends on the R and S bits in the R1: Control register (see "R1:
Control register," beginning on page 58).
Value Meaning Description
0 0 No access Any access generates a domain fault.
0 1 Client Accesses are checked against the access permission bits in the section or
page descriptor.
1 0 Reserved Reserved. Currently behaves like no access mode.
1 1 Manager Accesses are not checked against the access permission bits, so a
permission fault cannot be generated.
Table 41: Domain Access Control register, access control bits
AP S R Privileged permissions User permissions
0 0 0 0 No access No access
Table 42: Interpreting access permission (AP) bits