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PCI timing
816
NS9750 Hardware Reference
PCI timing
Note:
All AC characteristics are measured with 10pF, unless otherwise noted.
Table 471 and Table 472 describe the values shown in the PCI timing diagrams (Figure
121 through Figure 127).
Notes:
1 Parameters same for bussed and point-to-point signals.
2 CLOAD = 10pf on all outputs
3 pci_clk_out high and low times specified as 50% of the clock period +/-1 ns.
Parameter Description Min Max Units Notes
P1 pci_clk_in to signal valid delay 2 9 ns 1,2
P2 Input setup to pci_clk_in 5 ns 1
P3 Input hold from pci_clk_in 0 ns
P4 pci_clk_in to signal active 2 ns 2
P5 pci_clk_in to signal float 28 ns 2
P6 pci_clk_out high time 50%-1 50%+1 ns 3
P7 pci_clk_out low time 50%-1 50%+1 ns 3
P8 pci_clk_in cycle time 30 ns
P9 pci_clk_in high time 11 ns
P10 pci_clk_in low time 11 ns
Table 471: PCI timing characteristics