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Static memory controller
138
NS9750 Hardware Reference
Figure 50 shows a single external memory write transfer with two wait states
(
WA IT WR =2). One AHB wait state is added. Table 67 provides the timing parameters.
Table 68 describes the transactions for Figure 50.
WAITWEN 0
WAITTURN N/A
Cycle Description
T0 AHB address provided to memory controller.
T0-T1 AHB transaction processing.
T1-T4 Arbitration of AHB memory ports.
T4-T5 Static memory transfer 0, address, chip select, and control signals
submitted to static memory.
Write data is read from the AHB memory port.
Write enable inactive.
T5-T6 Write enable taken active.
Write data submitted to static memory.
Static memory writes the data.
T6-T7 Static memory writes the data.
Write enable taken inactive.
T7-T8 Static memory control signals taken inactive.
Table 66: External memory 0 wait state write
Timing parameters Value
Table 65: Static memory timing parameters