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Memory timing
806
NS9750 Hardware Reference
Static RAM asynchronous page mode read, WTPG = 1
Figure 114: Static RAM asynchronous page mode read, WTPG = 1 timing
WTPG = 1
WTRD = 2
If the PB field is set to 1, all four byte_lane signals will go low for 32-bit,
16-bit, and 8-bit read cycles.
The asynchronous page mode will read 16 bytes in a page cycle. A 32-bit bus
will do four 32-bit reads, as shown (3-2-2-2). A 16-bit bus will do eight 16-
bit reads (3-2-2-2-3-2-2-2) per page cycle, and an 8-bit bus will do sixteen
8-bit reads (3-2-2-2-3-2-2-2-3-2-2-2-3-2-2-2) per page cycle. 3-2-2-2 is the
example used here, but the WTRD and WTPG fields can set them
differently.
Notes:
1 The length of the first cycle in the page is determined by the WTRD field.
2 The length of the 2nd, 3rd, and 4th cycles is determined by the WTPG field.
3 This is the starting address. The least significant two bits will always be ‘00.’
4 The least significant two bits in the second cycle will always be ‘01.’
5 The least significant two bits in the third cycle will always be ‘10.’
6 The least significant two bits in the fourth cycle will always be ‘11.’
7 If the PB field is set to 0, the byte_lane signal will always be high during a read cycle.
Note-1 Note-2 Note-2 Note-2
M24M23
M28M27
M20M19
M18M18M17
M26
M25
M26
M25
Note-3 Note-4 Note-5 Note-6
Note-7
CPU clock / 2
data<31:0>
addr<27:0>
st_cs_n<3:0>
oe_n
byte_lane<3:0>