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Ethernet Control and Status registers
354
NS9750 Hardware Reference
Back-to-Back Inter-Packet-Gap register
Address: A060 0408
Register bit assignment
Bits Access Mnemonic Reset Description
D31:07 N/A Reserved N/A N/A
D06:00 R/W IPGT 0x00 Back-to-back inter-packet-gap
Programmable field that indicates the nibble time offset
of the minimum period between the end of any
transmitted frame to the beginning of the next frame.
Full-duplex mode
Register value should be the appropriate period in
nibble times minus 3.
Recommended setting is 0x15 (21d), which
represents the minimum IPG of 0.96 uS (in 100
Mbps) or 9.6uS (in 10 Mbps).
Half-duplex mode
Register value should be the appropriate period in
nibble times minus 6.
Recommended setting is 0x12 (18d), which
represents the minimum IPG of 0.96 uS (in 100
Mbps) or 9.6 uS (in 10 Mbps).
Table 213: Back-to-Back Inter-Packet-Gap register
Reserved
IPGT
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved