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NS9750 Hardware Reference
Figure 151 shows the layout of the NS9750, for use in setting up the board.
Figure 151: NS9750 BGA layout
MDC
AF23
D21
DCSn_2
12
AE19
IRDYn
VSS
AF3
D11
BLSn_0
B15
AD12
VDDS
AF7
CKE_2
GPIO18
GPIO11
GPIO1
TCK
VDDC
VDDC
DQM_0
1
T4
LCD_CLK
AD1
U23
AE22
ST_OEn
D
GPIO13
SCSn_0
RESETn
AB3
AA23
V3
GPIO49
D13
A13
GPIO10
SPLL_DG
AE16
RXDV
AE5
AD22
REQn_1
AD2
C22
C
H3
N2
M3
VDDC = CORE = 1.5V
GPIO47
AF26
D14
A25
C24
(GND)
GPIO5
VSS
VDDS
VSS
AD8
AF4
D15
R23
VDDC
AD10
VDDC
VDDC
TXD_2 BSTR_2
GPIO16
A10
TRSTn
M26
U24
AF6
GPIO45
CASn
D7
J
AF12
AD5
R26
K25
AA24
V4
INTBn
A26
A21
A17
GPIO24
14
AE11
GPIO6
D6
G3
T2
A12
D16
SPLL_AG
AF15
VSS = GROUND RETURN
(NC1)
AB1
TXCLK
B26
C14
VSS
GPIO35
DQM_3
E4
D5
M2
D17
VSS
AD31
VDDS
GPIO27
B7
DCSn_0
BSTR_4
A19
M23
VDDS
TXD_1
GPIO31
AC24
D20
G23
AC16
H25
U25
AD5
BLSn_2
K26
U2
AD17
AD26
C1M1
K24
AB4
RXD_0
AE25
D8
AD13
A18
VDDS
(NC4)
AC7
C3
D0
B9
C7
H1
N
R2
T3
VSS
VDDS
VSS
U
J3
D19
J26
VDDS
VDDS
TXD_3
AD23
SCSn_2
D30
F23
BSTR_3
T25
AD9
N24
VDDC
U26
AE23
DCSn_1
M4
GPIO21
GPIO15
A9
D20
AD15
U3
FRAMEn
GNTn_2
NS9750, 352 BGA
A6
A8
AA2
AA25
D8
B24
A18
AF10
AD18
I2C_SDA
(NC3)
RXD_1
AC4
CKE_1
R
VSS
W1
D15
8
B
M25
VSS
AE6
AE3
V
G24
GPIO22
P23
VDDS
VDDS
V1.1
A5
AF11
P24
VDDS
RXER
AF8
D10
GPIO4
A16
AD13
AD20
VDDC
TXEN
B22
AD10
AD17
U4
AD16
RST_DONE
AD30 D3
GPIO23
AA3
AA26
AD1
G4H4
P2
(GND)
C19
(NC2)GPIO46
C25
E26
VSS
VDDS
GPIO41
21
P1
RXCLK
VDDS
VSS
H2
B14
AC12
TRDYn
DEVSELn
VDDS
VDDS
V1
GPIO34
D17
2
AF13
B10
AE15
A20
N26
VDDC
TXER
GPIO40
C26
A14
N23
W23
IDSEL
AF22
INTAn
A
F2
AC14
A27
AF17
AF18
Y23
PCI_CKO
SCSn_3
D18
6
9
(NC5)
C4
D24
AC15
J25
VSS(GND)
PCI_CKI
GPIO48
GPIO43
E2
N3
AD3
VSS
AF9
GPIO28
T
TA_STB
B12
VDDS
VDDS
W
D1
C21
D9
C10
N25
VDDS
AD7
RSC_IN
A11
A25VDDC
GPIO36
AE8
AD25
CKO_3
D25
B23
A26
T26
AC20
W24
AD28
AD23
4
Top View, Balls Facing Down
R4
L3
T1
AC18
P25
Y24
D4
G1 E1
B20
(NC6)
AA4
CBEn_2
AC22
E3
(GND)
AE9
AD24
AC1
K4
AD7
VSS
AC9
D28
WEn
C11
11
D14
GPIO7
C18
VDDS
VDDS
GPIO33
Y
D23
VDDC
AD6
PCI_RSTn
INTCn
GPIO44
CKI_0
A24
AE10
16
AF20
VDDC
W25
AD19
AC8
B3
D29
5
J
1
SPLL_AV
H26
R25
Y25
AD25 D12
B4
K1
(NC7)
Y2
USB_X1
GPIO26
20
(GND)
Y1AA1
AD21
AD9
AD4
CKI_1DQM_1
CKO_1
L1
J2
GPIO12
TMS
VSS
VSS
C23
D13
B11
CBEn_1
VDDS
AA
C2
K
AD14
A20
VDDS
NC1 INTDn
M
GPIO25
AF16 B16
AE20
VDDC
PHY_INTn
D26
D23
D26
AC11
AD0
L25
VDDC
W26
REQn_2
CRS
AC6
F4
AD12
AD15
I2C_SCL
Y26
F
F1
CKE_0
A3
M24
(NC8)
Y3
GPIO32
GPIO42
B1
CKO_2
A12
AD8
PERRn
(GND)
AD22
A0
A1
H
D18
L24
VSS
VSS
B25
A9
A21
VDDS
VDDS
SCANENn
AF25
24
R1
P3
C13
B19
AC17AE17
VDDC
AD3
AE2
A8
P
A7
VDDC
V23
NC2
A23
D9
A7
N4
W2
AD18 D2
D2
C9
AC13
AC19
(NC9)
Y4
AC5
AF2
AB
F24
G26
CKI_3
GPIO3
A1
T23 L23
(GND)
AD26
D22
A15
AD11
AC10
VSS
COL
23
A6
DCSn_3
7
CKO_0
CBEn_0
H24
VDDS
AE24
AE1
F26
AE12
B17
D31
AD21
AE26
26
K2
C15
D1
VDDC
U1
USB_DP
D27
D22
CKE_3
B18
VDDC
AD20
AC25
D6
A22
AD11
W3
AC
D7
F25
BISTENn
NC3
AB23
GPIO30
PLLTSTn
25
TDO
GPIO2
(GND)
CBEn_3
GPIO29
A22
AE13
VSS
RXD_3
G25
G2
CKI_2
USB_X2
AF14 AE14
A4
R24
VSS
A3
GPIO38
AE21
3
DY_PWRn
AD19
C16
A15
VDDC
VDDS
AC21
AC3
SPLL_DV
T24
K23
VDDC
C5
E
GPIO9
W4
V24
AE7
AC23
DQM_2
B8
D3
SYS_X2
BSTR_1
AD4
AB24
REQn_3
AD
22
E24
N1
D11
GPIO19
18
C20
(GND)
AD24
A4
B6
VSS
D19
D12
A10
A16
GPIO8
AD6 VSS
A2
RXD_2
AC2
C6
SYS_X1
17
C17
AF1
F3
A5
SERRn
VDDC
VDDS
AB2
E23
D21
L2
(GND)
B13
RTCK
J24
VDDC
AC26
A24
K3
AD2
H23
V2
V25
AE
D25
C8
J4
GPIO14
STOPn
AB25
BLSn_3
G
P4
A23
15
A13
(VDDC)
AD27
L4
R3
A17
VSS
MDIO
AF24
D10
B21
D16
BSTR_0
C12
A2
A14
VSS
D4
L
GPIO17
VDDS
TXD_0
AF5
USB_DMGPIO39
TDI
A11
PAR
L26
VDDC
A19
P26V26
AF21
AD29
BLSn_1
J23
AD14
( ) = Reserved
AB26
AE4
AF
RASn
D5
B2
GPIO20
10
13
19
(VDDS)
GNTn_1GNTn_3
B5
SCSn_1
GPIO0
VDDS = I/O = 3.3V
GPIO37
D24
E25
(GND)
AE18
AD16
AF19
VSS