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About the PCI-to-AHB Bridge
414
NS9750 Hardware Reference
PCI Vendor ID register
Read-only value. To change this value, use the
VENDOR_ID field in the PCI
Configuration 0 register in the PCI arbiter (see page 428).
PCI Device ID register
Read-only value. To change this value, use the
DEVICE_ID field in the PCI
Configuration 0 register in the PCI arbiter (see page 428).
PCI Command register
The default value of this register is
0x0000. Table 255 describes the register fields.
1 These entries are standard read-only PCI configuration registers that are initialized using registers
in the PCI arbiter (see "PCI bus arbiter," beginning on page 418).
Bits Description Type
D15:10 Reserved Hardwired to 0
D09 Fast back-to-back Hardwired to 0; the device cannot generate
fast back-to-back cycles.
D08 SERR# R/W
D07 Address stepping Hardwired to 0
D06 Parity error response R/W
D05 VGA palette snooping Hardwired to 0
D04 Master MWI (set to 0 for NS9750) R/W
D03 Special cycle response Hardwired to 0
D02 Bus master (set to 1 for NS9750) R/W
D01 Memory enable (set to 1 for NS9750) R/W
D00 IO enable (set to 0 for NS9750) R/W
Table 255: Command register
Register
number
[31:24] [23:16] [15:08] [07:00]
Table 254: PCI/bridge configuration registers